This application relates generally to phase lock loop technology and more particularly to a phase detection system for phase lock loop circuits. More particularly still, the present invention relates to a phase detector that reduces dead band.
Phase lock loop circuits are prevalently used in many and various technologies. In general, a phase lock loop circuit receives an incoming data signal and analyzes that data signal to generate an output clock signal that is synchronized to the incoming data signal. Creating the synchronized output clock is highly beneficial as this synchronized clock signal can then be used in many different algorithms to further analyze and utilize the incoming data signal in a meaningful manner. For instance, if the incoming data signal must be sampled at a particular point in time in relation to the data signal itself, then it is important to identify the frequency and phase of the incoming data signal to allow for proper sampling of the data signal. Thus, the output clock signal is created with timing characteristics that correspond to the input signal such that the input data signal can be sampled at a meaningful time.
An exemplary phase lock loop system may be a component of a computer disc drive""s read channel timing recovery circuit. Phase lock loops are typically used in the disc drive industry to recover the read clock and to generate the write clock at a variety of frequencies depending on which data zones are used.
Phase lock loop circuits typically have a phase detector circuit that receives the data signal and a feedback clock signal. The feedback clock signal is representative, if not identical to the generated output clock signal in terms of phase and frequency. The typical phase detector compares these two input signals, in terms of phase and produces two output control signals xe2x80x9cpump upxe2x80x9d and xe2x80x9cpump downxe2x80x9d in response to the comparison. These xe2x80x9cpump upxe2x80x9d and xe2x80x9cpump downxe2x80x9d signals are conducted to a charge pump, which, using integration techniques, produces a proportional voltage signal in relation to the received pump up and pump down signals. The voltage signal produced by the charge pump is then conducted to a voltage-controlled oscillator (VCO), which in turn, generates an oscillating voltage clock signal based on the received voltage value. The resulting oscillating signal typically becomes the phase-lock-loop generated clock signal used for future analysis.
A known problem with phase detectors occurs when an input pulse is missing on the data signal. Without added intelligence to handle such a situation, the phase detector, as a result of comparing a pulse with a non-pulse, conducts a signal to the charge pump signifying that the two signals are significantly out of phase, i.e., a pump up or pump down condition. The charge pump reacts to these control signals and remains in a charged state and thus creates an output voltage that may be inappropriate. Prior art solutions to this problem involve using digital logic to test for missing pulses and disable the phase detector during the missing pulse time. Consequently, detecting the missing pulse situation allows the phase detector to modify the signal delivered to the charge pump so that it may xe2x80x9ccoastxe2x80x9d and not substantially impact the output of the VCO during that time frame.
In order to provide a phase detector having integral, missing-pulse-detection logic, the phase detector itself is typically made up of digital logic. Phase detectors that incorporate such digital logic, however, suffer from a unique problem known as xe2x80x9cdeadband.xe2x80x9d That is, as the data signal and the feedback clock signal achieve an xe2x80x9cin-phasexe2x80x9d condition, wherein each signal has essentially the same phase, and thus should be locked, the resulting control signals from the digital phase detector become very small pulses, e.g., approximately five nanosecond pulses. These very small pulses must turn on the analog components of the charge pump to create a proportional voltage, i.e., a voltage proportional to the pulse width. However, when the pulses are so small, the charge pump may not adequately turn on, due to turn on time of the circuit components associated with the charge pump, e.g., three nanosecond turn on time.
When the charge pump fails to turn on, no output control signal is conducted to the VCO, which may react by forcing the clock signal more out of phase. Consequently, typical digital phase lock loop systems continually force the clock signal from being in a phase lock situation to a non-phase lock situation and then back to a phase lock situation. In other words, as the system becomes closer to being in a locked or optimal condition, the smaller the pulses become and therefore prevent the charge pump from turning on which allows the clock to drift out of phase. As the clock drifts out of phase, the pulses become larger and the charge pump turns on to force the clock back in phase, etc. This situation is also known as jitter wherein the clock signal is continuously forced in and out of a phase lock situation.
In order to better understand the present invention, the following brief discussion of a typical prior-art, digital phase detector is provided. FIG. 2 illustrates such a digital phase detector circuit 200, which includes a first flip flop 202 and a second flip flop 204. Flip flop 202 receives a digital data signal 206, while flip flop 204 receives the feedback clock signal 208. The Q outputs of the flip flops 202 and 204 are buffered by buffers 210 and 212, respectively, and conducted to a charge pump (not shown), as pump up signal 214 and pump down signal 216, respectively. The charge pump, to produce a control voltage, evaluates the widths of the resulting signals on 210 and 212.
The xe2x80x9cQxe2x80x9d output signals of flip flops 202 and 204 are conducted to NAND gate 218, which conducts a signal to effectively clear the flip flops 202 and 204. Due to inherent delays in the various components, such as 202, 204 and 218 the flip flops 202 and 204 are not cleared immediately following a situation wherein both of the inputs to the NAND gate 218 become high. Consequently, small pulses are still conducted to the charge pump on signals 214 and 216.
FIG. 3 illustrates sample waveforms relating to the prior-art, phase detector 200 shown in FIG. 2. As shown, feedback clock signal 208 and data signal 206 relate to digital pulse signals. Also as shown in FIG. 3, pump down signal 216 conducts a pulse following the rising edge of the feedback clock signal 208. The delay 220 between the rising edges of signals 208 and 216 relates to the time delay in the flip flop 204 and buffer 212. Similarly, the pump up signal 214 conducts a pulse following the rising edge of the data signal 206. The delay 222 between the rising edges of signals 206 and 214 relates to the propagation time delay in the flip flop 202 and buffer 210. The difference in phase may be determined by analyzing the difference in the rising edges of the two signals 206 and 208 or, as shown by determining the delay 224 between the rising edges of the two output signals 214 and 216.
Since the flip flops 202 and 204 are cleared by the NAND gate 218 as soon as the two Q output signals are high, the width of pulse 226 is determined by the delay associated with the NAND gate 218 and delay in clearing the flip flop 202. This width may be extremely short and thus the pulse width may be very small. Importantly, this small pulse may not be high long enough to turn on the components of the charge pump such that the charge pump does not alter its output in response to the small pulse. Moreover, as shown in FIG. 3, as the signals 206 and 208 become more in phase, the width of pulses on 216 become almost as narrow as the pulses on 214. Consequently, the charge pump may not read any signal from the phase detector which prevents any correction from taking place, which condition is known as a dead band, i.e., when the charge pump has no gain. The lack of correction, or dead band, causes the clock signal 208 to become more out of phase. The constant movement in and out of phase is known as jitter.
One common solution to the dead band or jitter problem is to use high-performance or high-speed components in the charge pump. These components have a reduced turn-on time characteristic, which allows the charge pump to more appropriately handle the very slim phase detector pulses. Unfortunately however, these components are expensive. Moreover, since these components still have to be turned on, the slim pulses may still not provide enough time for the components to adequately turn on.
Another solution relates to integrating these high performance components onto the same chip as the phase detector, so as to reduce other delays associated with buffering the output signal of a phase detector chip as the pump control signal is conducted to another chip housing the analog charge pump. Such integration increases cost and significantly reduces the flexibility in designing other components that work in connection with the digital phase detector or the analog charge pump.
It is with respect to these and other considerations that the present invention has been made.
The present invention relates to a digital phase detector that conducts pump up and pump down control signals to a charge pump, wherein each signal has pulses that have a substantially 50/50 duty cycle characteristic when the two input signals, i.e., the input data signal and the feedback clock signal, are substantially in phase. Thus, the pump up and pump down control signals relate to relatively large, in time, pulses that allow the charge pump time to turn on its components. This substantially 50/50 duty cycle output reduces, if not eliminates, inherent problems related to the turn-on delays of the charge pump while maintaining a locked condition. Furthermore, the digital nature of the phase detector allows for the addition of intelligence to detect and handle other situations, such as missing data pulse situation.
An embodiment of the invention relates to a phase detector for detecting the phase difference between an incoming data signal and a fed-back clock signal. In this embodiment, the phase detector comprises an edge detector for detecting an edge of the data signal and the fed-back clock signal and producing at least one control signal. The control signals are latched by a latch that receives the control signals and latches a plurality of output signals in response to the at least one control signal, wherein the combination of the output signals provides a signal indicative of the difference in the phase between the data signal and the fed-back clock signal. In another embodiment, the combination of the output signals relates to an integration function performed by a charge pump as part of a phase lock loop.
In an embodiment, one of the output signals is held high for approximately half a duty cycle plus an amount of time related to the difference in phase between the data signal and the fed-back clock signal. In this embodiment, the other output signal is similarly held high for approximately half a duty cycle minus an amount of time related to the difference in phase between the data signal and the fed-back clock signal. Hence, the duty cycles for the output control signals approximates a 50/50 duty cycle when the data signal and the fed-back clock signal are substantially in phase, wherein a 50/50 duty cycle relates to each pulse having a width that is substantially equal to half the time between rising edges of each pulse.
In yet another embodiment, the phase detector further incorporates a missing pulse detector. The missing pulse detector may be a flip flop and which effectively disables the phase detector when a missing pulse is detected.
Still another embodiment relates to a method of generating an output clock signal based on an input data signal, wherein the method has acts of detecting a phase difference between the input data signal and a fed-back clock signal and conducting at least two control signals representative of the phase difference to a charge pump wherein the control signals representing the phase difference comprise digital pulse signals having a relatively equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase. The method may further comprise generating a voltage signal in response to the at least two control signals and conducting the voltage signal to a voltage controlled oscillator, which produces an oscillating output clock signal based on the voltage signal received. Additionally, the method act of generating a voltage signal may be performed by a charge pump that integrates the at least two control signals, and wherein the voltage signal is minimal when the input data signal and the fed-back clock signal are substantially in phase. Furthermore, the method may also relate to detecting a missing pulse in the data signal and modifying the at least two control signals in response to detecting the missing pulse to reduce the effect on the charge pump.
These and various other features as well as advantages which characterize the present invention will be apparent from a reading of the following detailed description and a review of the associated drawings.